8P34S1208 Datasheet | Renesas

Description The 8P34S1208 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals. The 8P34S1208 supports fail-safe operation and is characterized to operate from a 1.8V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1208 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise. Features - Eight low skew, low additive jitter LVDS output pairs - Two selectable, differential clock input pairs - Differential CLK, n CLK pairs can accept the following differential input levels: LVDS, CML - Maximum input clock frequency: 1.5GHz - LVCMOS/LVTTL interface levels for the control input select pin - Output skew: 20ps (typical) - Propagation delay: 400ps (maximum) - Low propagation delay variation across temperature for 1PPS applications - Low additive phase jitter, RMS; f REF = 156.25MHz, VPP = 1V, 12k Hz- 20MHz: 34fs (typical) - Device current consumption (IDD): - 120m A typical: 1.8V - 132m A typical: 2.5V - Full 1.8V or 2.5V supply voltage - Lead-free (Ro HS 6), 28-Lead VFQFPN packaging - -40°C to +85°C ambient operating temperature - Supports case temperature up to +105°C - Supports PCI Express Gen1- 5 Block Diagram VREF0 CLK0 n CLK0 CLK1 n CLK1 Voltage Reference VDD f REF VDD VREF1 Voltage Reference Q0 n Q0 Q1 n Q1 Q2 n Q2 Q3 n Q3 Q4 n Q4 Q5 n Q5 Q6 n Q6 Q7 n Q7 Q7 n Q7 Pin Assignment Q1 n Q1 Q2 n Q2 Q3 n Q3 21 20 19 18 17 16...