8P34S1208 Overview
The 8P34S1208 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals. The 8P34S1208 supports fail-safe operation and is characterized to operate from a 1.8V or 2.5V power supply.
8P34S1208 Key Features
- Eight low skew, low additive jitter LVDS output pairs
- Two selectable, differential clock input pairs
- Differential CLK, nCLK pairs can accept the following
- Maximum input clock frequency: 1.5GHz
- LVCMOS/LVTTL interface levels for the control input select pin
- Output skew: 20ps (typical)
- Propagation delay: 400ps (maximum)
- Low propagation delay variation across temperature for 1PPS