8P34S1102 Description
The 8P34S1102 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals. The 8P34S1102 supports fail-safe operation and is characterized to operate from a 1.8V or 2.5V power supply.
8P34S1102 Key Features
- Two low skew, low additive jitter LVDS output pairs
- One differential clock input pair
- Differential CLK, nCLK pairs can accept the following
- Maximum input clock frequency: 51.2GHz
- Output skew: 3ps (typical)
- Propagation delay: 400ps (maximum)
- Low additive phase jitter, RMS; fREF = 156.25MHz
- Device current consumption (IDD)
- 40mA typical: 1.8V
- 50mA typical: 2.5V