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8V19N491-24 - Jitter Attenuator and Clock Synthesizer

Datasheet Summary

Description

The 8V19N491-24 is a fully integrated FemtoClock NG Jitter Attenuator and Clock Synthesizer that is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards.

Features

  • High-performance clock RF-PLL with support for JESD204B/C.
  • Optimized for low phase noise: -155dBc/Hz (1MHz offset; 245.76MHz clock, and 491.52MHz VCXO).
  • Integrated phase noise of 80fs RMS typical (12k-20MHz).
  • Dual-PLL architecture.
  • First PLL stage with external VCXO for clock jitter attenuation.
  • Second PLL with internal FemtoClockNG PLL: 2457.6MHz.
  • Six output channels with a total of 16 outputs, organized in:.
  • Four JESD204B channels (device clock and.

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Datasheet Details

Part number 8V19N491-24
Manufacturer Renesas
File Size 2.27 MB
Description Jitter Attenuator and Clock Synthesizer
Datasheet download datasheet 8V19N491-24 Datasheet
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Full PDF Text Transcription

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FemtoClock® NG Jitter Attenuator and Clock Synthesizer 8V19N491-24 Datasheet Description The 8V19N491-24 is a fully integrated FemtoClock NG Jitter Attenuator and Clock Synthesizer that is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics.
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