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8V19N491-36 - NG Jitter Attenuator and Clock Synthesizer

Datasheet Summary

Description

The 8V19N491-36 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer.

The device is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards.

Features

  • High-performance clock RF-PLL with support for JESD204B.
  • Optimized for low phase noise: -152.5dBc/Hz (800kHz offset; 245.76MHz clock).
  • Integrated phase noise of 65fs RMS typical (12kHz.
  • 20MHz) at 737.28MHz.
  • Dual-PLL architecture.
  • First PLL stage with external VCXO for clock jitter attenuation.
  • Second PLL with internal FemtoClock NG PLL: 3686.4MHz.
  • Six output channels with a total of 19 outputs, organized in:.
  • Four JESD204B channels (device cloc.

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Datasheet Details

Part number 8V19N491-36
Manufacturer Renesas
File Size 1.90 MB
Description NG Jitter Attenuator and Clock Synthesizer
Datasheet download datasheet 8V19N491-36 Datasheet
Additional preview pages of the 8V19N491-36 datasheet.

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Full PDF Text Transcription

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FemtoClock® NG Jitter Attenuator and Clock Synthesizer 8V19N491-36 Datasheet Description The 8V19N491-36 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer. The device is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics.
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