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9DBL0442 Datasheet PDF

Renesas Electronics 9DBL0442

The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family. The 9DBL0442 / 9DBL0452 supports PCIe Gen1–4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines.
Part No. 9DBL0442
Datasheet 9DBL0442 Download
Manufacturer
Renesas Electronics
Description 3.3V PCIe Zero Delay Buffer
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9DBL0442 datasheet page 1 preview

DESCRIPTION

The 9DBL04P2 can be factory programmed with a user-defined power up default SMBus configuration. Typical Application PCIe Gen1–4 clock distribution for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Output

FEATURES

● Four 1–200 MHz Low-Power HCSL (LP-HCSL) DIF pairs
● 9DBL0442 default ZOUT = 100Ω
● 9DBL0452 default ZOUT = 85Ω
● 9DBL04P2 factory programmable defaults
● Easy AC-coupling to other logic families, see Renesas application note AN-891 Key Specifications
● PCIe Gen1–4 CC compliant in ZDB mode
● PCIe Gen2 SRIS compliant in ZDB mode
● Supports PCIe Gen2–3 SRIS in fanout mode
● DIF cycle-to-cycle jitter < 50ps
● DIF output-to-output skew < 50ps
● Bypass mode additive phase jitter is 0 ps typical rms for PCIe
● Bypass mode additive phase jitter 160fs rms typical at 156.25MHz (1.5MHz to 10MHz)

FEATURES

● Direct connection to 100Ω (xx42) or 85Ω (xx52) transmission lines; saves 16 resistors compared to standard PCIe devices
● 132mW typical power con...
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