9DBL0442 - 3.3V PCIe Zero Delay Buffer

Renesas

General Description

The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family.

4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems.

Key Features

Four 1.
200 MHz Low-Power HCSL (LP-HCSL) DIF pairs.
9DBL0442 default ZOUT = 100Ω.
9DBL0452 default ZOUT = 85Ω.
9DBL04P2 factory programmable defaults.
Easy AC-coupling to other logic families, see Renesas.

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9DBL0442 3.3v pcie zero delay buffer by Renesas - Datasheet Preview

Datasheet Details

Part number	9DBL0442
Manufacturer	Renesas
File Size	401.12 KB
Description	3.3V PCIe Zero Delay Buffer
Datasheet	9DBL0442 Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
9DBL0442	4-Output 3.3V PCIe Zero-delay Buffer	IDT
9DBL0443	4-output 3.3V LP-HCSL Zero-Delay Buffer	IDT
9DBL04	4-output 3.3V PCIe Zero-delay Buffer	IDT
9DBL0452	4-Output 3.3V PCIe Zero-delay Buffer	IDT
9DBL0453	4-output 3.3V LP-HCSL Zero-Delay Buffer	IDT

Other Datasheets by Renesas

Part Number	Description
9DBL0442	Zero-Delay/Fanout Buffer
9DBL0442C	2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers
9DBL0452	3.3V PCIe Zero Delay Buffer
9DBL0452	Zero-Delay/Fanout Buffer
9DBL0452C	2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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4-Output 3.3V PCIe Zero Delay Buffer 9DBL0442 / 9DBL0452 Datasheet Description The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family. The 9DBL0442 / 9DBL0452 supports PCIe Gen1–4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL04P2 can be factory programmed with a user-defined power up default SMBus configuration.