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9QXL2001C - PCIe Clock Buffer

Description

The 9QXL2001C is an enhanced-performance 9QXL2001B with ultra-low-additive phase jitter for PCIe Gen5, Gen6 and UPI applications.

The 9QXL2001C also reduces propagation delay by approximately 50% with respect to the 9QXL2001B.

Common Clocked (CC) Independent R

Features

  • 8 OE# pins provide hardware control of 8 outputs.
  • SMBus allows software control of each output.
  • 25MHz Side-Band Interface allows real-time control of all 20 outputs.
  • Outputs remain Low/Low when powered up with floating input clock.
  • Power Down Tolerant (PDT) inputs.
  • 85Ω Low-Power HCSL (LP-HCSL) outputs:.
  • Eliminate 80 resistors, saving 130mm2 of area.
  • Power consumption reduced by 50%.
  • 9 selectable SMBus addresses.
  • Spread spectrum compatibl.

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Other Datasheets by Renesas

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9QXL2001B PCIe Clock Buffer
9QXL2000B 20-output very-low-additive phase jitter fanout buffer

Full PDF Text Transcription

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9QXL2001C 20-Output Enhanced DB2000QL Datasheet Description The 9QXL2001C is an enhanced-performance 9QXL2001B with ultra-low-additive phase jitter for PCIe Gen5, Gen6 and UPI applications. The 9QXL2001C also reduces propagation delay by approximately 50% with respect to the 9QXL2001B. PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference (IR) – SRNS, SRIS Applications ▪ Servers, Storage, Networking, Accelerators ▪ Key Specifications ▪ Output-to-output skew: < 50ps ▪ PCIe Gen5 additive phase jitter: 6fs RMS ▪ PCIe Gen6 additive phase jitter: 4fs RMS ▪ DB2000Q additive phase jitter: 10fs RMS ▪ 12kHz–20MHz additive jitter: 23fs RMS at 156.25MHz ▪ Propagation delay: 1.4ns typical VDDA3.
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