HD74HC564P Datasheet | Renesas

Description These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only that the former has inverting outputs and the latter has noninvertering outputs. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features - High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 p F) - High Output Current: Fanout of 15 LSTTL Loads - Wide Operating Voltage: VCC = 2 to 6 V - Low Input Current: 1 µA max - Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) - Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC564P HD74HC574P DILP-20 pin PRDP0020AC-B (DP-20NEV) HD74HC564FPEL SOP-20 pin (JEITA) HD74HC574FPEL PRSP0020DD-B (FP-20DAV) HD74HC564RPEL SOP-20 pin (JEDEC) PRSP0020DC-A (FP-20DBV) Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) - EL (2,000 pcs/reel) EL (1,000 pcs/reel) Function Table Inputs Outputs Output Control Clock Data HD74HC564 HD74HC574...