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ICS8305I-02 - LVCMOS-to-LVCMOS Fanout Buffer

General Description

The ICS8305I-02 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer.

The ICS8305I-02 has selectable clock inputs that accept either differential or single-ended input levels.

Key Features

  • Four LVCMOS/LVTTL outputs, (two banks of two LVCMOS outputs).
  • Selectable differential CLK, nCLK pair or LVCMOS_CLK input.
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL.
  • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL.
  • Maximum output frequency: 250MHz.
  • Output skew: 100ps (maximum).
  • Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 3.3V/1.5V.
  • -40°C to 85.

📥 Download Datasheet

Datasheet Details

Part number ICS8305I-02
Manufacturer Renesas
File Size 1.31 MB
Description LVCMOS-to-LVCMOS Fanout Buffer
Datasheet download datasheet ICS8305I-02 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Low Skew, 1-to-4 Multiplexed Differential/ ICS8305I-02 LVCMOS-to-LVCMOS Fanout Buffer PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2016 DATA SHEET General Description The ICS8305I-02 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305I-02 has selectable clock inputs that accept either differential or single-ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.