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R9A06G150 - ASSP

General Description

Maximum operating frequency: up to 100 MHz Andes AndesCore™ D25F: Revision: 2.4.0 AndeStar V5 instruction-set architecture (ISA) RISC-V RV32I base integer instruction set RISC-V C standard extension for compressed instructions RISC-V M st

Key Features

  • RISC-V Andes D25F Core.
  • RISC-V instruction-set architecture (RV32I).
  • Maximum operating frequency: 100 MHz.
  • Andes Physical Memory Protection unit (Andes PMP) with 16 regions.
  • Debug and Trace: RISC-V External Debug Support.
  • Debug Port: JTAG.
  • Memory.
  • 256-KB code flash memory.
  • 16-KB data flash memory (100,000 program/erase (P/E) cycles).
  • 128-KB SRAM.
  • Connectivity.
  • Serial Communications Interface (SCI) × 2.
  • Asynchronous interfaces.

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Datasheet R9A06G150 ASSP for voice command and control based on RISC-V R01DS0405EJ0100 Rev.1.00 Nov 18, 2022 Leading-performance 100 MHz RISC-V Andes D25F core, 256 KB code flash memory with background operation, 16 KB Data flash memory, and 128 KB SRAM with Parity. High-integration with Quad SPI.