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UPD48011318 - Low Latency DRAM

General Description

double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor eDRAM memory cell.

Key Features

  • 1 cycle 600MHz DDR Muxed Address.
  • Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power.
  • Training sequence for per-bit deskew.
  • Selectable Refresh Mode: Auto or Overlapped Refresh.
  • Programmable PVT-compensated output impedance.
  • Programmable PVT-compensated on-die input termination.
  • PLL for improved input jitter tolerance and wide output data valid window Ordering Information Part number Cycle C.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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μPD48011318 μPD48011336 1.1G-BIT Low Latency DRAM-III Common I/O Burst Length of 2 Datasheet R10DS0012EJ0200 Rev.2.00 Feb 01, 2013 Description The μPD48011318 is a 67,108,864-word by 18-bit and the μPD48011336 is a 33,554,432-word by 36-bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor eDRAM memory cell. The Low Latency DRAM-III chip is a 1.1Gbit DRAM capable of a sustained throughput of approximately 43.2 Gbps for burst length of 2 (approximately 51.2 Gbps for applications implementing error correction), excluding refresh overhead and data bus turn-around With a bus speed of 600 MHz, a burst length of 2, and a tRC of 13.