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uPD46185092B - 18M-BIT QDR II SRAM 2-WORD BURST OPERATION

General Description

The μPD46185092B is a 2,097,152-word by 9-bit, the μPD46185182B is a 1,048,576-word by 18-bit and the μPD46185362B is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

Key Features

  • 1.8 ± 0.1 V power supply.
  • 165-pin.

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Datasheet Details

Part number uPD46185092B
Manufacturer Renesas
File Size 613.15 KB
Description 18M-BIT QDR II SRAM 2-WORD BURST OPERATION
Datasheet download datasheet uPD46185092B Datasheet

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Other Datasheets by Renesas

Part Number Description
uPD46185094B 18M-BIT QDR II SRAM 4-WORD BURST OPERATION
uPD46185084B 18M-BIT QDR II SRAM 4-WORD BURST OPERATION
uPD46185182B 18M-BIT QDR II SRAM 2-WORD BURST OPERATION
uPD46185184B 18M-BIT QDR II SRAM 4-WORD BURST OPERATION
uPD46185362B 18M-BIT QDR II SRAM 2-WORD BURST OPERATION

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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μPD46185092B μPD46185182B μPD46185362B Datasheet 18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION R10DS0112EJ0200 Rev.2.00 Nov 09, 2012 Description The μPD46185092B is a 2,097,152-word by 9-bit, the μPD46185182B is a 1,048,576-word by 18-bit and the μPD46185362B is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The μPD46185092B, μPD46185182B and μPD46185362B integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration.