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uPD46185184B - 18M-BIT QDR II SRAM 4-WORD BURST OPERATION

Download the uPD46185184B datasheet PDF. This datasheet also covers the uPD46185084B variant, as both devices belong to the same 18m-bit qdr ii sram 4-word burst operation family and are provided as variant models within a single manufacturer datasheet.

General Description

R10DS0113EJ0200 Rev.2.00 Nov 09, 2012 The μPD46185084B is a 2,097,152-word by 8-bit, the μPD46185094B is a 2,097,152-word by 9-bit, the μPD46185184B is a 1,048,576-word by 18-bit and the μPD46185364B is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS te

Key Features

  • 1.8 ± 0.1 V power supply.
  • 165-pin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (uPD46185084B-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number uPD46185184B
Manufacturer Renesas
File Size 567.19 KB
Description 18M-BIT QDR II SRAM 4-WORD BURST OPERATION
Datasheet download datasheet uPD46185184B Datasheet

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Other Datasheets by Renesas

Part Number Description
uPD46185182B 18M-BIT QDR II SRAM 2-WORD BURST OPERATION
uPD46185084B 18M-BIT QDR II SRAM 4-WORD BURST OPERATION
uPD46185092B 18M-BIT QDR II SRAM 2-WORD BURST OPERATION
uPD46185094B 18M-BIT QDR II SRAM 4-WORD BURST OPERATION
uPD46185362B 18M-BIT QDR II SRAM 2-WORD BURST OPERATION

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
μPD46185084B μPD46185094B μPD46185184B μPD46185364B Datasheet 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION Description R10DS0113EJ0200 Rev.2.00 Nov 09, 2012 The μPD46185084B is a 2,097,152-word by 8-bit, the μPD46185094B is a 2,097,152-word by 9-bit, the μPD46185184B is a 1,048,576-word by 18-bit and the μPD46185364B is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The μPD46185084B, μPD46185094B, μPD46185184B and μPD46185364B integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.