RKnanoC Datasheet | Rockchip

RKnano C Datasheet Rockchip Confidential ROCKCHIPS PRODUCT DATASHEET RKNano C Revision 1.7 Apr. 2013 4/3/2013 RKnano C Datasheet Rockchip Confidential 1. Overview RKnano C is a low-cost, low-power, high-efficiency digital multimedia chip which is based on ARM low power processor architecture with hardware accelerator. It is designed for portable audio product applications such as MP3 player etc. RKnano C can support decode for various types of audio standards such as MP3/WMA /OGG/FLAG/AAC etc. Because of build-in audio hardware accelerator, RKnano C can achieve audio decode at a very low system frequency, this can save chip power consumption. By providing a plete set of peripheral interface, RKnano C can support very flexible applications, including NAND Flash, LCDC, USB OTG, SD/MMC, I2C, I2S, SPI, UART, PWM etc. 2. Features z System Operation - ARM processor - AHB-lite bus connection - Selectable booting method ‹ Boot from NAND FLASH ‹ Boot from e MMC flash ‹ Boot from SPI NOR flash z Memory Organization - Internal 224KB SRAM for IRAM and DRAM - Embedded 64KB ROM for decoder and system code z Processor - ARM Cortex-M3 low power core ‹ A Thumb instruction set subset ‹ Banked Stack Pointer (SP) only ‹ Hardware divide instructions, SDIV and UDIV (Thumb 32-bit instructions) ‹ Handler and Thread modes ‹ Thumb and Debug states ‹ Interruptible-continued LDM/STM, PUSH/POP for low interrupt latency ‹ Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit - Nested Vectored Interrupt Controller (NVIC) ‹ 26 external interrupts. ‹ 8-level priority of interrupt z Clock & Power Management - One on-chip PLL, system main clock can be PLL clock or OSC input clock - Support different main clock and internal AHB Bus clock ratio: 1:1, 1:2, 1:3, 1:4, up to 1:8 modes - Support different AHB Bus clock and ARM system tick clock ratio: 1:2, 1:3, 1:4, up to 1:8 modes - Support different AHB Bus clock and ARM APB Bus clock...