RKnanoC Description
RKnanoC Datasheet Rockchip Confidential ROCKCHIPS PRODUCT DATASHEET RKNanoC Revision 1.7 Apr. 2013 1 4/3/2013 RKnanoC Datasheet Rockchip Confidential 1. Overview RKnanoC is a low-cost, low-power, high-efficiency digital multimedia chip which is based on ARM low power processor architecture with hardware accelerator.
RKnanoC Key Features
- ARM processor
- AHB-lite bus connection
- Selectable booting method Boot from NAND FLASH Boot from eMMC flash Boot from SPI NOR flash
- Internal 224KB SRAM for IRAM and DRAM
- Embedded 64KB ROM for decoder and system code
- ARM Cortex-M3 low power core A Thumb instruction set subset Banked Stack Pointer (SP) only Hardware divide instruc
- Nested Vectored Interrupt Controller (NVIC)
- One on-chip PLL, system main clock can be PLL clock or OSC input clock
- Support different main clock and internal AHB Bus clock ratio
- Support different AHB Bus clock and ARM system tick clock ratio