BU2092 Overview
For the BU2090 / F / FS, data input is shifted to the 12-bit internal shift register on the rising edge of a clock pulse. On the falling edge of the pulse, if the DATA pin is HIGH, the data in the shift register is output in parallel to Q0 to Q11. For the BU2092 / F / FV, shift data read at the rising edge of CLOCK is output in parallel to Q0 to Q11 at the rising edge of LCK.
BU2092 Key Features
- 1) Low power dissipation. 2) Operating voltages ranging from 2.7 to 5.5V. 3) Output is Nch open drain. 4) High output wi
- 0.3 ~ + 7.0
- 25 ~ + 75
- 55 ~ + 125 VSS
- 0.3 ~ VDD + 0.3 VSS ~ 25.0
- Remended operating conditions
- Block diagram
- Pin descriptions