SR5017 Datasheet | SMSC

STANDARD MICROSYSTEMS CORPORATION SR5017 SR5018 Quad Static Shift Right/Shift Left Shift Register Last In First Out Buffer LIFO Features o PLAMOS® N-Channel Silicon Gate Technology. PIN CONFIGURATION o Quad 81 bit or Quad 133 bit o Directly patible with T2L, MOS o Operation Guaranteed from DC to INPUTD RID RECD GND 1.0MHz o Recirculate logic on-chip OUTPUTD OUTPUTC o Single +5.0V power supply o Low clock input capacitance o Single phase clock at T2L levels o Clear function CLEAR OUTPUT A URCON INPUTC INPUTB OUTPUTB o 16-pin Ceramic DIP Package INPUT A RECABC APPLICATIONS OBi-Directional Printer CLOCK Vcc o puters-Push Down Stack-LIFO o Buffer data storage-memory buffer o Delay lines-delay line processing o Digital filtering o Telemetry Systems o Terminals o Peripheral Equipment REC CONTROL ABC ">---4..........-1 BLOCK DIAGRAM OUTPUT A OUTPUTC INPUT A ~I---t 1------< INPUT C ~--< RECIRC.INPUT D ~J-.-.1"-~ REC. CONTROL D INPUTB...