M36L0R7060T1 Datasheet | STMicroelectronics

Features - Multichip package - 1 die of 128 Mbit (8 Mb x16, Multiple Bank, Multilevel, Burst) Flash memory - 1 die of 64 Mbit (4 Mb x16) Pseudo SRAM Supply voltage - VDDF = VCCP = VDDQF = 1.7 to 1.95 V - VPPF = 9 V for fast program Electronic signature - Manufacturer Code: 20h - Top Device Code M36L0R7060T1: 88C4h - Bottom Device Code M36L0R7060B1: 88C5h Package - ECOPACK® FBGA - TFBGA88 (ZAQ) 8 x 10 mm - - - .. Security - 64 bit unique device number - 2112 bit user programmable OTP Cells Block locking - All blocks locked at power-up - Any bination of blocks can be locked with zero latency - WPF for Block Lock-Down - Absolute Write Protection with VPPF = VSS - Flash memory - Synchronous / Asynchronous Read - Synchronous Burst Read mode: 54 MHz, 66 MHz - Random Access: 70 ns, 85 ns Synchronous Burst Read Suspend Programming time - 2.5 µs typical word program time using Buffer Enhanced Factory Program mand Memory organization - Multiple Bank memory array: 8 Mbit banks - Parameter Blocks (top or bottom location) mon Flash Interface (CFI) 100 000 program/erase cycles per block Dual operations - program/erase in one Bank while read in others - No delay between read and write operations - - - - - PSRAM Access time: 70 ns Asynchronous Page Read - Page Size: 4, 8 or 16 words - Subsequent read within page: 20 ns Low power features - Automatic Temperature-pensated Self Refresh (TCR) - Partial Array Self-Refresh (PASR) - Deep Power-Down (DPD) mode Synchronous Burst Read/Write - -...