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M48Z12 - 16 Kbit (2 Kb x 8) ZEROPOWER SRAM

General Description

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Key Features

  • Integrated, ultra low power SRAM and powerfail control circuit.
  • Unlimited WRITE cycles.
  • READ cycle time equals WRITE cycle time.
  • Automatic power-fail chip deselect and WRITE protection.
  • WRITE protect voltages (VPFD = power-fail deselect voltage):.
  • M48Z02: VCC= 4.75 to 5.5 V; 4.5 V ≤ VPFD ≤ 4.75 V.
  • M48Z12: VCC= 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V.
  • Self-contained battery in the CAPHAT™ DIP package.
  • Pin and function compatible with JEDEC standard.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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M48Z02 M48Z12 5 V, 16 Kbit (2 Kb x 8) ZEROPOWER® SRAM Features ■ Integrated, ultra low power SRAM and powerfail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages (VPFD = power-fail deselect voltage): – M48Z02: VCC= 4.75 to 5.5 V; 4.5 V ≤ VPFD ≤ 4.75 V – M48Z12: VCC= 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V ■ Self-contained battery in the CAPHAT™ DIP package ■ Pin and function compatible with JEDEC standard 2 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect 24 1 PCDIP24 Battery CAPHAT™ June 2011 Doc ID 2420 Rev 9 1/22 www.st.com 1 Contents Contents M48Z02, M48Z12 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .