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M48Z35AV - 256 Kbit (32 Kbit x 8) ZEROPOWER SRAM

Key Features

  • Integrated, ultra low power SRAM, power-fail control circuit, and battery.
  • READ cycle time equals WRITE cycle time ).
  • Battery low flag (BOK) t(s.
  • Automatic power-fail chip deselect and WRITE cprotection du.
  • WRITE protect voltage: ro(VPFD = power-fail deselect voltage) P.
  • M48Z35AV: 2.7 V ≤ VPFD ≤ 3.0 V te.
  • Self-contained battery in the CAPHAT™ DIP lepackage o.
  • Packaging includes a 28-lead SOIC and sSNAPHAT® top (to be ordered separately) Ob.
  • Pin and f.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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M48Z35AV 5.0 V or 3.3 V, 256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM Not recommended for new design Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time )■ Battery low flag (BOK) t(s■ Automatic power-fail chip deselect and WRITE cprotection du■ WRITE protect voltage: ro(VPFD = power-fail deselect voltage) P– M48Z35AV: 2.7 V ≤ VPFD ≤ 3.