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M74HC280 - 9 BIT PARITY GENERATOR

General Description

The M74HC280 is a high-speed CMOS 9-bit parity generator fabricated with silicon gate C2MOS technology.

It is composed of nine data inputs (A to I) and odd/even parity outputs (ΣODD and ΣEVEN).

The nine data inputs control the output conditions.

Key Features

  • High-speed: tPD = 22 ns (typ. ) at VCC = 6 V.
  • Low power dissipation: ICC = 4 μA (max. ) at TA = 25 °C.
  • High noise immunity: VNIH = VNIH = 28 % VCC (min).
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min. ).
  • Balanced propagation delays: tPLH ≅ tPHL.
  • Wide operating voltage range: VCC (opr) = 2 V to 6 V.
  • Pin and function compatible with 74 series 280.
  • ESD performance.
  • HBM: 2 kV.
  • MM: 200 V.
  • CDM: 1.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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M74HC280 9-bit parity generator Datasheet - production data SO14 TSSOP14 Features • High-speed: tPD = 22 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIH = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating voltage range: VCC (opr) = 2 V to 6 V • Pin and function compatible with 74 series 280 • ESD performance – HBM: 2 kV – MM: 200 V – CDM: 1 kV Description The M74HC280 is a high-speed CMOS 9-bit parity generator fabricated with silicon gate C2MOS technology. It is composed of nine data inputs (A to I) and odd/even parity outputs (ΣODD and ΣEVEN). The nine data inputs control the output conditions.