MK50H25 - HIGH SPEED LINK LEVEL CONTROLLER

Product Overview

ST Microelectronics

Part number	MK50H25
Manufacturer	STMicroelectronics
File Size	515.27 KB
Description	HIGH SPEED LINK LEVEL CONTROLLER
Datasheet	MK50H25 Datasheet
Additional preview pages of the MK50H25 datasheet.

(Continued) For added flexibility a transparent mode provides an HDLC transport mechanism without link layer support.

System clock rate up to 33 MHz (MK50H25 33), 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst length. DMA transfer rate of up to 13.3 Mbytes/sec using optional 5 SYSCLK DMA cycle (150 nS) at 33 MHz SYSCLK. Complete Level 2 implementation compatible with X.25 LAPB, ISDN LAPD, X.32, and X.75 Protocols. Handles all error recovery, sequencing, and S and U frame control. Pin-for-pin.

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Published: May 7, 2005 |