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MK50H27 - Signalling System 7 Link Controller

Datasheet Summary

Description

Pin out for 52 pin PLCC is shown in brackets.

PIN(S) 2-9 40-47 [2-10 44-51] 10 [11] TYPE IO/3S DESCRIPTION The time multiplexed Data/Address bus.

Features

  • Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements Pin-for-pin and architecturally compatible with MK50H25 (X.25/LAPD), MK50H29 (SDLC), and MK50H28(Frame Relay). System clock rates up to 33 MHz (MK50H27 33), or 25 MHz (MK50H27 - 25). Data rate up to 4 Mbps continuous for SS7 protocol processing, 20 Mbps for transparent HDLC m.

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Datasheet preview – MK50H27

Datasheet Details

Part number MK50H27
Manufacturer STMicroelectronics
File Size 417.62 KB
Description Signalling System 7 Link Controller
Datasheet download datasheet MK50H27 Datasheet
Additional preview pages of the MK50H27 datasheet.

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Full PDF Text Transcription

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MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements Pin-for-pin and architecturally compatible with MK50H25 (X.25/LAPD), MK50H29 (SDLC), and MK50H28(Frame Relay). System clock rates up to 33 MHz (MK50H27 33), or 25 MHz (MK50H27 - 25). Data rate up to 4 Mbps continuous for SS7 protocol processing, 20 Mbps for transparent HDLC mode, or up to 51 Mbps bursted (gapped data clocks, non-continuous data). On chip DMA control with programmable burst length. DMA transfer rate of up to 13.3 Mbytes/sec using optional 5 SYSCLK DMA cycle (150 nS) at 33 MHz SYSCLK.
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