DESCRIPTION
A signal on the D INPUT is transfered to the Q OUTPUT during the positive going transition of the clock pulse. PIN CONNECTION AND IEC LOGIC SYMBOLS June 1999 1/10 74VHC74 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND FUNCT ION Asyncronous Reset Direct Input Data Input Clock Input (LOW-to-HIGH, EdgeTriggered) Asyncronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage 4, 10 5, 9 6, 8 7 14 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC TRUTH TABLE INPUTS CLR L H L H H H X:Don’t Care OUT PUT S D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn F UNCTION CLEAR PRESET PR H L L H H H NO CHANGE LOGIC DIAGRAMS Thislogic diagram has notbe used to estimate propagation delays 2/10 74VHC74 ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperatu...
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