DESCRIPTION
s t(s) The CLOCK input is active on the rising edge. Both LOAD and CLEAR inputs are active LOW. c Presetting is synchronous on the rising edge of u the clock, the function is cleared asynchronously. DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC161B1R M74HC161M1R T&R M74HC161RM13TR M74HC161TTR Two enable inputs (TE and PE) and CARRY output are provided to enable easy cascading of counters, which facilities easy implementation of N-bit counters without using external gates. All inputs are equipped with protection circuits against static discharge and transient excess voltage. Obsolete Prod PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC161 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION 1 CLEAR Asynchronous Master Reset 2 CLOCK Clock Input (LOW to HIGH, Edge-triggered) 3, 4, 5, 6 A, B, C, D Data Inputs 7 PE Count Enable Input 10 TE Count Enable Carry Input 9 LOAD Parallel Enable Input 14, 13, 12, 11 ) 15 t(s 8 c 16 QA...
STMicroelectronics
