DESCRIPTION
Signals applied to the data inputs (D1 D4) are stored at the respective flip-flops on the positive going transition of the clock input, only DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC173B1R M74HC173M1R T&R M74HC173RM13TR M74HC173TTR when both clock control inputs (G1 and G2) are held low. The reset feature is asynchronous and active high. The stored data are provided on each output only when both output control inputs (M and N) are held low, otherwise the outputs go to the high-impedance state. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC173 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE CLEAR CLOCK X X X X H X L L L L L X : Don’t Care Z : High Impedance DATA ENABLE G1 G2 X X X X X X X X H X X H L L L L PIN DESCRIPTION
PIN No 1, 2 3, 4, 5, 6 7 9, 10 14, 13, 12, 11 15 8 16 SYMBOL M, N 1Q to 4Q CLOCK G1, G2 1D to 4D NAME AND FUNCTION Output Ena...
STMicroelectronics
