DESCRIPTION
bs - These four flip-flops are controlled by a clock input t(s) (CLOCK) and a clear input (CLEAR). All inputs are equipped with protection circuits against static discharge and transient excess voltage. Obsolete Produ PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 M74HC175 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION 1 CLEAR Asynchronous Master Reset (Active Low) 2, 7, 10, 15 1Q to 4Q Flip-Flop Outputs 3, 6, 11, 14 1Q to 4Q Complementary Flip-Flop Outputs 4, 5, 12, 13 1D to 4D Data Inputs 9 CLOCK Clock Input (LOW to HIGH, edge triggered) 8 GND Ground (0V) t(s) TRUTH TABLE roduc CLEAR L P H lete H o H s X : Don’t Care INPUTS D X L H X Obsolete Product(s) - Ob LOGIC DIAGRAM CLOCK X 16 Vcc Positive Supply Voltage OUTPUTS Q Q L H L H H L Qn Qn FUNCTION NO CHANGE This logic diagram has not be used to estimate propagation delays 2/11 M74HC175 ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Inpu...