DESCRIPTION
Information signals applied to D inputs are transferred to the Q output on the positive going edge of the clock pulse. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 M74HC174 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS CLEAR D CK L X X H L H H H X X : Don’t Care LOGIC DIAGRAM PIN DESCRIPTION
PIN No 1 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 9 8 16 SYMBOL CLEAR NAME AND FUNCTION Asynchronous Master Reset (Active Low) Q0 to Q5 Flip-Flop Outputs D0 to D5 CLOCK GND Vcc Data Inputs Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltage OUTPUTS Q L L H Qn FUNCTION CLEAR NO CHANGE This logic diagram has not to be used to estimate propagation delays 2/11 M74HC174 ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Dio...
STMicroelectronics
