DESCRIPTION
The HC4024 is a 7 stage Counter. This devices is incremented on the falling edge (negative transition) of the input clock, and all its outputs are reset to a low level by applying a logical high on their reset input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1992 NC = No Internal Connection 1/11 M54/M74HC4024 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE CLOCK X CLEAR H L L X: DON’T CARE OUTPUT STATE ALL OUTPUTS = ”L” NO CHANGE ADVANCE TO NEXT STATE LOGIC DIAGRAM 2/11 M54/ M74HC4024 PIN DESCRIPTION
PIN No 1 2 12, 11, 9, 6, 5, 4, 3 8, 10, 13 7 14 SYMBOL CLOCK RESET Q1 to Q7 NC GND V CC NAME AND FUNCTION Clock Input (HIGH to LOW, Edge-triggered) Reset Input (Active HIGH) Parallel Outputs Not Connected Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOL ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Cur...
STMicroelectronics
