STMicroelectronics PSD835G2V
Flash PSD
FEATURES
● Flash in-system programmable (ISP) peripheral for 8-bit MCUs Dual bank Flash memories – 4 Mbits of Primary Flash memory (8 uniform sectors, 64 Kbyte) – 256 Kbits of secondary Flash memory with 4 sectors – Concurrent operation: READ from one memory while erasing and writing the other 64 Kbit of battery-backed SRAM 52 reconfigurable I/O ports Enhanced JTAG serial port PLD with macrocells – Over 3000 gates of PLD: CPLD and DPLD – CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs) – DPLD - user defined internal chip select decoding 52 individually configurable I/O port pins They can be used for the following functions: – MCU I/Os – PLD I/Os – Latched MCU address output – Special function I/Os. – I/O ports may be configured as open-drain outputs. In-system programming (ISP) with JTAG – Built-in JTAG compliant serial port allows full-chip In-System Programmability – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable...