PSD835G2V Overview
11 1.1 In-system programming (ISP) via JTAG . 11 1.1.1 1.1.2 1.1.3 First time programming . 11 Inventory build-up of pre-programmed devices.
PSD835G2V Key Features
- 4 Mbits of Primary Flash memory (8 uniform sectors, 64 Kbyte)
- 256 Kbits of secondary Flash memory with 4 sectors
- Concurrent operation: READ from one memory while erasing and writing the other 64 Kbit of battery-backed SRAM 52 reconfi
- Over 3000 gates of PLD: CPLD and DPLD
- CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs)
- user defined internal chip select decoding 52 individually configurable I/O port pins They can be used for the following
- MCU I/Os
- PLD I/Os
- Latched MCU address output
- Special function I/Os