SPC570S50E1 Datasheet | STMicroelectronics

SPC570S40E1, SPC570S40E3, SPC570S50E1, SPC570S50E3 32-bit Power Architecture® microcontroller for automotive ASILD applications - production data e TQFP100 (14 x 14 x 1.0 mm) e TQFP64 (10 x 10 x 1.0 mm) Features - AEC-Q100 qualified - High performance e200z0h dual core - 32-bit Power Architecture technology CPU - Core frequency as high as 80 MHz - Single issue 4-stage pipeline in-order execution core - Variable Length Encoding (VLE) - Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation - Up to 48 KB on-chip general-purpose SRAM - Multi-channel direct memory access controller (e DMA paired in lockstep) with 16 channels - prehensive new generation ASILD safety concept - Safety of bus masters (core+INTC, DMA) by delayed lockstep approach - Safety of storage (Flash, SRAM) by mainly ECC - Safety of the data path to storage and periphery by mainly End-to-End EDC (E2E EDC) - Clock and power, generation and distribution, supervised by dedicated monitors - Fault Collection and Control Unit (FCCU) for collection and reaction to failure notifications - Memory Error Management Unit (MEMU) for collection and reporting of error events in memories - Boot time MBIST and LBIST for latent faults - Check of safety mechanisms availability and error reaction path functionality by dedicated mechanisms - Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST - Further measures on dedicated peripherals (e.g. ADC supervisor) - Junction temperature sensor - 8-region system memory protection unit (SMPU) with process ID support (tasks isolation) - Enhanced SW watchdog - Cyclic redundancy check (CRC) unit - Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for putational...