STMicroelectronics SPC570S50E3
32-bit Power Architecture microcontroller
| Part No. | SPC570S50E3 |
|---|---|
| Datasheet | SPC570S50E3 Download |
| Manufacturer |  STMicroelectronics |
| Description | 32-bit Power Architecture microcontroller |
| Buy | Stock & Price |
FEATURES
● AEC-Q100 qualified● High performance e200z0h dual core – 32-bit Power Architecture technology CPU – Core frequency as high as 80 MHz – Single issue 4-stage pipeline in-order execution core – Variable Length Encoding (VLE)
● Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
● Up to 48 KB on-chip general-purpose SRAM
● Multi-channel direct memory access controller (eDMA paired in lockstep) with 16 channels
● Comprehensive new generation ASILD safety concept – Safety of bus masters (core+INTC, DMA) by delayed lockstep approach – Safety of storage (Flash, SRAM) by mainly ECC – Safety of the data path to storage and periphery by mainly End-to-End EDC (E2E EDC) – Clock and power, generation and distribution, supervised by dedicated monitors – Fault Collection and Control Unit (FCCU) for collection and reaction to failure notifications – Memor...
