DESCRIPTION
The members of An on-chip Figure 1. Logic Diagram VCC RST Table 1. Signal Names CLK RST I/O VCC GND Clock Reset Data Input / Output Supply Voltage ST1335 ST1336 ST1355 CLK I/O GND Ground AI03106b October 1999 Complete data available under NDA. 1/3 ST1335, ST1336, ST1355 Figure 2. Memory Map 0 16 Physical EEPROM Cells 32 bits 0 16 masked bits Circuit Identification Area Card Identification Area (ID) RAM1 (Write-Only) (RN) (ST1335, ST1355) 32 48 bits Data Area (CD) 40 bits 8 bits 16 bits (Counters and Transport Code) Reserved Area (RA) Certificate (CER) Issuer-Defined Area (ST1336) 64 bits Authentication Secret Key (SK) (ST1335, ST1355) 64 104 112 128 Physical EEPROM Cells 192 Reserved Area (RA) 256 260 264 288 Physical EEPROM Cells 32 bits Anti-Tearing Flags 320 4 bits 4 bits 24 bits Signature Fuses Unused 56 bits User-Defined Area 376 AI03385 Note: 1. The write-only RAM area (RN) is applicable only for the User Configuration. address counter provides an internal address space of up to 512 bits.
STMicroelectronics
