STA1295 Overview
7 2.1 Application processor . 7 2.2 Memory architecture . 7 2.2.1 Embedded memory.
STA1295 Key Features
- AEC-Q100 qualified Grade 3
- ARM® Single or Dual Core Cortex® A7 up to 650 MHz with NEON instructions and FPU
- Memory organization
- L1 Cache: 32 KB instruction, 32 KB data
- L2 Cache: 256 KB
- 768 KB embedded SRAM
- 16/32-bit DDR3L interface at 660 MHz
- Serial Quad IO NOR interface
- 16-bit Parallel NAND Controller
- 32-bit watchdog timer