STIDP880 Datasheet | STMicroelectronics

STi DP880 i DP to LVDS converter Data brief Features - - - - - - - Supports Asynchronous Scrambler Seed Reset (ASSR) for premium contents reception Configurable through I2C host interface Supports Spread Spectrum for EMI/RFI reduction Robust interoperability - supports FFC and UTP type cables Low power operation; 20 m W standby Package - 164 LFBGA (12 x 12 mm/0.8 mm pitch) - HF and Ro HS pliant Power supply voltages - 3.3 V I/O; 1.2 V core ESD - 2 KV HBM, 200 V MM, 600V CDM Internal Display Port (i DP) receiver - pliant with proposed i DP specification - 3.24 Gbps per lane - 1, 2, or 4 lanes - HPD pulse assertion as per proposed i DP standard Supports video timings up to 1920 x 1080 (FHD) 120 Hz/10-bit color Interface patibility with wide range of panels - Quad LVDS interface up to 100 MHz per channel (400 MHz pixel rate) - High speed dual-link LVDS up to 150 MHz per channel (300 MHz pixel rate) - Supports JEIDA, non-JEIDA, VESA pixel data mappings - - - - Applications http://..net/ - High refresh rate TV/monitor panel interface i DP Input 4 Main Lanes HPD Internal Display Port Receiver Bus Formatter LVDS Outputs Q-LVDS output I2C Host Interface December...