SPP2305D Datasheet | SYNC POWER

P-Channel Enhancement Mode MOSFET DESCRIPTION The SPP2305D is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density , DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other battery powered circuits, and low in-line power loss are needed in a very small outline surface mount package. APPLICATIONS z Power Management in Note book z Portable Equipment z Battery Powered System z DC/DC Converter z Load Switch z DSC z LCD Display inverter Features ‹ -15V/-3.5A,RDS(ON)= 70mΩ@VGS=-4.5V ‹ -15V/-3.0A,RDS(ON)= 85mΩ@VGS=-2.5V ‹ -15V/-2.0A,RDS(ON)=105mΩ@VGS=-1.8V ‹ Super high density cell design for extremely low RDS (ON) ‹ Exceptional on-resistance and maximum DC current capability ‹ SOT-23 package design PIN CONFIGURATION(SOT-23) PART MARKING S05YW 2011/01/03 Ver.1 Page 1 P-Channel Enhancement Mode MOSFET PIN DESCRIPTION Pin 1 2 3 ORDERING INFORMATION Part Number SPP2305DS23RG ※ Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 ) ※ SPP2305DS23RG : Tape Reel ; Pb - Free Package SOT-23 Part Marking S05YW Symbol G S D Description Gate Source Drain ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted) Parameter Drain-Source Voltage Gate - Source Voltage Continuous Drain Current(TJ=150℃) Pulsed Drain Current Continuous Source Current(Diode Conduction) Power Dissipation Operating Junction Temperature Storage Temperature Range Thermal Resistance-Junction to Ambient TA=25℃ TA=70℃ TA=25℃ TA=70℃ Symbol VDSS VGSS ID IDM IS PD TJ TSTG RθJA Typical -15 ±12 -3.5 -2.8 -10 -1.6 1.25 0.8 150 -55/150 120 Unit V V A A A W ℃ ℃ ℃/W 2011/01/03 Ver.1 Page 2 P-Channel Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TA=25℃ Unless otherwise noted) Parameter Static Drain-Source Breakdown Voltage Gate Threshold Voltage Gate...