Datasheet Summary
CMOS SDRAM
128Mbit SDRAM
4M x 8Bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.0 Aug. 1999
- Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 Aug. 1999
4M x 8Bit x 4 Banks Synchronous DRAM
Features
- JEDEC standard 3.3V power supply
- LVTTL patible with multiplexed address
- Four banks operation
- MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
- All inputs are sampled at the positive going edge of the system clock.
- Burst read single-bit write operation
- DQM for masking
- Auto & self refresh
- 64ms refresh period...
