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K4S641632H - 64Mb H-die SDRAM

General Description

Revision 1.5 (February, 2004) - Corrected typo.

Revision 1.6 (March, 2004) - Modified Pin Description.

Revision 1.7 (May, 2004) - Added Note 5.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM (x4,x8) & L(U)DQM (x16) for masking.
  • Auto & self refresh.
  • 64ms r.

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Datasheet Details

Part number K4S641632H
Manufacturer Samsung Electronics
File Size 145.06 KB
Description 64Mb H-die SDRAM
Datasheet download datasheet K4S641632H Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM 64Mb H-die SDRAM Specification Revision 1.8 August 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.8 August 2004 SDRAM 64Mb H-die (x4, x8, x16) Revision History Revision 0.0 (May, 2003) - Target spec release Revision 0.1 (July, 2003) - Preliminary spec release Revision 0.2 (August, 2003) - Modified IBIS characteristic. Revision 1.0 (September, 2003) - Finalized. Revision 1.1 (September, 2003) - Corrected IBIS Specification. Revision 1.2 (October, 2003) - Deleted speed 7C at x4/x8. Revision 1.3 (October, 2003) - Deleted AC parameter notes 5. Revision 1.4 (November, 2003) - Modified Pin Function description. Revision 1.5 (February, 2004) - Corrected typo. Revision 1.