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K7P323674C - 1Mx36 & 2Mx18 SRAM

This page provides the datasheet information for the K7P323674C, a member of the K7P321874C 1Mx36 & 2Mx18 SRAM family.

Datasheet Summary

Description

The K7P323674C and K7P321874C are 37,748,736 bit Synchronous Pipeline Mode SRAM.

It is organized as 1,048,576 words of 36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.

Features

  • 1Mx36 or 2Mx18 Organizations.
  • 1.8 or 2.5V VDD/1.5V ~1.8VDDQ.
  • HSTL Input and Output Levels.
  • Differential, HSTL Clock Inputs K, K.
  • Synchronous Read and Write Operation.
  • Registered Input and Registered Output.
  • Internal Pipeline Latches to Support Late Write. Preliminary www. DataSheet4U. com 1Mx36 & 2Mx18 SRAM.
  • Byte Write Capability(four byte write selects, one for each 9bits).
  • Synchronous or Asynchronous Output E.

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Datasheet preview – K7P323674C

Datasheet Details

Part number K7P323674C
Manufacturer Samsung Electronics
File Size 481.02 KB
Description 1Mx36 & 2Mx18 SRAM
Datasheet download datasheet K7P323674C Datasheet
Additional preview pages of the K7P323674C datasheet.

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Full PDF Text Transcription

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K7P323674C K7P321874C Preliminary www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM 32Mb C-die LW SRAM Specification 119BGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.
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