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KM641001A - CMOS SRAM

General Description

The KM641001A is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits.

The KM641001A uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.

Key Features

  • Fast Access Time 15, 20ns(Max. ).
  • Low Power Dissipation Standby (TTL) : 25mA(Max. ) (CMOS) : 8mA(Max. ) Operating KM641001A - 15 : 125mA(Max. ) KM641001A - 20 : 120mA(Max. ).
  • Single 5.0V±10% Power Supply.
  • TTL Compatible Inputs and Outputs.
  • I/O Compatible with 3.3V Device.
  • Fully Static Operation - No Clock or Refresh required.
  • Three State Outputs.
  • Standard Pin Configuration KM641001AJ : 28-SOJ-400A PIN.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com PRELIMINARY CMOS SRAM KM641001A Document Title 256Kx 4 High Speed Static RAM(5V Operating), Evolutionary Pin Out. Operated at Commercial Temperature Range. Revision History Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary Release to final Data Sheet. 2.1. Delete Preliminary Update D.C and A.C parameters. 3.1. Update D.C parameters Previous spec. Items (15/17/20ns part) Icc 190/180/170mA Isb 30mA Isb1 10mA 3.2. Update A.C parameters Previous spec. Items (15/17/20ns part) tCW 12/12/13ns tAW 12/12/13ns tWP1(OE=H) 12/12/13ns tDW 8/9/10ns Draft Data Jan. 18th, 1995 Apr. 22th, 1995 Remark Design Target Preliminary Rev. 2.0 Feb. 29th, 1996 Final Rev. 3.0 Jul.