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KM736V687A - 64Kx36-Bit Synchronous Burst SRAM

Datasheet Summary

Description

The KM736V687A is 2,359,296 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system.

And with CS1 high, ADSP is blocked to control signals.

It can be organized as 64K words of 36 bits.

Features

  • Synchronous Operation.
  • On-Chip Address Counter.
  • Write Self-Timed Cycle.
  • On-Chip Address and Control Registers.
  • VDD= 3.3V+0.3V/-0.165V Power Supply.
  • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Power Down State via ZZ Signal.
  • Asynchronou.

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Datasheet Details

Part number KM736V687A
Manufacturer Samsung Semiconductor
File Size 469.08 KB
Description 64Kx36-Bit Synchronous Burst SRAM
Datasheet download datasheet KM736V687A Datasheet
Additional preview pages of the KM736V687A datasheet.

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Full PDF Text Transcription

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KM736V687A Document Title 64Kx36-Bit Synchronous Burst SRAM 64Kx36 Synchronous SRAM Revision History Rev. No. 0.0 0.1 History Initial draft Change DC Characteristics. ICC value from 320mA to 250mA at -7. ICC value from 300mA to 230mA at -8. ICC value from 280mA to 200mA at -9. ISB value from 90mA to 70mA at -7. ISB value from 80mA to 60mA at -8. ISB value from 70mA to 50mA at -9. ISB1 value from 30mA to 20mA ISB2 value from 30mA to 20mA Final spec release. Add VDDQ Supply voltage( 2.5V ) Min tOH Parameter Change : from 2.0ns to 3.0ns Min tLZC Parameter Change : from 0ns to 3ns Draft Date July. 03. 1998 Sep. 14. 1998 Remark Preliminary Preliminary 1.0 2.0 3.0 Nov. 16. 1998 Dec. 02. 1998 Dec. 17.
Published: |