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KM736V795 - 128Kx36 Synchronous SRAM

Datasheet Summary

Description

The KM736V795 is a 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Features

  • Synchronous Operation.
  • 2 Stage Pipelined operation with 4 Burst.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • VDD= 3.3V+0.3V/-0.165V Power Supply.
  • I/O Supply Voltage 2.5V+0.4V/-0.13V.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Power Down State via ZZ Signal.
  • LBO Pin.

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Datasheet preview – KM736V795

Datasheet Details

Part number KM736V795
Manufacturer Samsung Semiconductor
File Size 321.68 KB
Description 128Kx36 Synchronous SRAM
Datasheet download datasheet KM736V795 Datasheet
Additional preview pages of the KM736V795 datasheet.

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Full PDF Text Transcription

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KM736V795 Document Title 128Kx36 Synchronous SRAM 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 0.1 History Initial draft Change DC characteristics VDD condition from VDD=3.3V+10%/-5% Change Input/output leackage currant from ±1µA to ±2µA Modify Read timing & Power down cycle timing. Change ISB2 value from 30mA to 20mA. Remove DC characteristics ISB1 - L ver.& ISB2 - L ver . Remove Low power version. Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.6V((pulse width≤tCYC/2) Change VIN max from 5.5V to VDD+0.5V Draft Date February. 02. 1998 February. 12. 1998 Remark Preliminary Preliminary 0.2 April. 14. 1998 Preliminary 0.3 May. 13. 1998 Change ISB2 value from 20mA to 30mA.
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