Datasheet4U Logo Datasheet4U.com

KM736V799 - 128Kx36 Synchronous SRAM

Datasheet Summary

Description

The KM736V799 is a 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Features

  • Synchronous Operation.
  • 2 Stage Pipelined operation with 4 Burst.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • VDD= 3.3V+0.165V/-0.165V Power Supply.
  • VDDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.

📥 Download Datasheet

Datasheet preview – KM736V799

Datasheet Details

Part number KM736V799
Manufacturer Samsung Semiconductor
File Size 297.84 KB
Description 128Kx36 Synchronous SRAM
Datasheet download datasheet KM736V799 Datasheet
Additional preview pages of the KM736V799 datasheet.

📁 Similar Datasheet

  • KM702 - Sensor (MEGATRON)
  • KM7101 - 4.9MHz Rail-to-Rail I/O Amplifier (Fairchild Semiconductor)
Other Datasheets by Samsung Semiconductor
  • KM736V790 - 128Kx36 Synchronous SRAM
  • KM736V795 - 128Kx36 Synchronous SRAM
  • KM736V747 - (KM736V747 / KM718V847) 128Kx36 & 256Kx18 Flow-Through NtRAM
  • KM736V749 - (KM736V749 / KM718V849) 128Kx36 & 256Kx18 Pipelined NtRAM
  • KM736V787 - 128Kx36 Synchronous SRAM
  • KM736V789 - 128Kx36 Synchronous SRAM
  • KM736V687 - 64Kx36-Bit Synchronous Burst SRAM
  • KM736V687A - 64Kx36-Bit Synchronous Burst SRAM

Full PDF Text Transcription

Click to expand full text
KM736V799 Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev. No 0.0 0.1 History Initial draft Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.6V(pulse width≤tCYC/2) Change VIH max from 5.5V to VDD+0.5V Change tCD from 3.2ns to 3.1ns at bin -50. Change tOE from 3.2ns to 3.1ns at bin -50. Change setup from 1.5ns to 1.4ns at bin -50. Change tCYC from 5.5ns to 5.4ns at bin -55. Change tCD from 3.5ns to 3.1ns at bin -55. Change tOE from 3.5ns to 3.1ns at bin -55. Change setup from 1.5ns to 1.4ns at bin -55. Add tCYC 175Mhz. Change ISB2 from 20mA to 30mA. Modify DC characteristics( Input Leakage Current test Conditions) form VDD=VSS to VDD to Max. Final Release. Add tCYC 225Mhz.
Published: |