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K4C89083AF - 288Mb x18 Network-DRAM2 Specification

General Description

K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells.

K4C89183AF is organized as 4,194,304-words x 4 banks x18 bits.

Key Features

  • Parameter CL = 4 tCK Clock Cycle Time (min) tRC Random Read/Write Cycle Time (min) tRAC Random Access Time (min) IDD1S Operating Current (single bank) (max) IDD2P Power Down Current (max) CL = 5 CL = 6 K4C89183AF F6 4.0 ns 3.5 ns 3.0ns 20.0 ns 20.0 ns 320mA 70mA FB 4.5 ns 3.75 ns 3.33 ns 22.5 ns 22.5 ns 300mA 65mA F5 5.0 ns 4.5 ns 4.0 ns 25 ns 25 ns 280mA 60mA.

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Full PDF Text Transcription for K4C89083AF (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4C89083AF. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com K4C89183AF 288Mb x18 Network-DRAM2 Specification Version 0.7 - 1 - REV. 0.7 Jan. 2005 K4C89183AF Revision History Version 0.0 (Oct. 2002) - First Rele...

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2005 K4C89183AF Revision History Version 0.0 (Oct. 2002) - First Release Version 0.01 (Nov. 2002) - Changed die revision from D-die to F-die - Corrected typo - Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram. Version 0.1 (Apr. 2003) - Added 800Mbps(400Mhz) product - Changed operating temperature from Ta to Tc. - Changed capacitance of ADDR/CMD/CLK From Min Addr/CMD/CLK 1.5 Max 2.5 Min 1.5 To Max 3.0 - Changed tDSS(DS input Falling Edge to Clock Setup Time) From F6 CL4 CL5 CL6 CL7 0.9 0.9 0.9 FB 0.9 0.9 0.9 F5 1.0 1.0 1.0 G7 0.75 0.75 0.75 0.75 F6 0.75 0.75 0.75 To FB 0.8 0.8 0.8 F5 1.0 1

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