K4X1G323PC-LG Datasheet PDF (32Mx32 Mobile DDR SDRAM) | Download Samsung semiconductor K4X1G323PC-LG

K4X1G323PC-LG - 32Mx32 Mobile DDR SDRAM

This page provides the datasheet information for the K4X1G323PC-LG, a member of the K4X1G323PC-L 32Mx32 Mobile DDR SDRAM family.

Description

Clock : CK and CK are differential clock inputs.

All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.

Internal clock signals are derived from CK/CK.

Features

VDD/VDDQ = 1.8V/1.8V.
Double-data-rate architecture; two data transfers per clock cycle.
Bidirectional data strobe(DQS).
Four banks operation.
Differential clock inputs(CK and CK).
MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave).
EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Fu.

Datasheet Details

Part number	K4X1G323PC-LG
Manufacturer	Samsung semiconductor
File Size	605.18 KB
Description	32Mx32 Mobile DDR SDRAM
Datasheet	K4X1G323PC-LG Datasheet
Additional preview pages of the K4X1G323PC-LG datasheet.

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Full PDF Text Transcription

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K4X1G323PC - L(F)E/G 32Mx32 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 ) • Internal Temperature Compensated Self Refresh • All inputs except data & DM are sampled at the positive going edge of the system clock(CK). www.DataSheet4U.com • Data I/O transactions on both edges of data strobe, DM for masking.

Published: May 16, 2010 |