K7A801809A Overview
The K7A803609A and K7A801809A are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 256K(512K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; Write cycles are internally self-timed and...
K7A801809A Key Features
- Synchronous Operation
- 2 Stage Pipelined operation with 4 Burst
- On-Chip Address Counter
- Self-Timed Write Cycle
- On-Chip Address and Control Registers
- 3.3V+0.165V/-0.165V Power Supply
- 5V Tolerant Inputs Except I/O Pins
- Byte Writable Function
- Global Write Enable Controls a full bus-width write
- Power Down State via ZZ Signal