Datasheet4U Logo Datasheet4U.com

K7A803609A - 256Kx36 & 512Kx18 Synchronous SRAM

Download the K7A803609A datasheet PDF. This datasheet also covers the K7A801809A variant, as both devices belong to the same 256kx36 & 512kx18 synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The K7A803609A and K7A801809A are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Key Features

  • Synchronous Operation.
  • 2 Stage Pipelined operation with 4 Burst.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • 3.3V+0.165V/-0.165V Power Supply.
  • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Powe.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K7A801809A_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Samsung Semiconductor

Part Number Description
K7A803609B 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
K7A803600B 256K x 36 & 512K x 18 Synchronous SRAM
K7A803601M 256Kx36 & 512Kx18 Synchronous SRAM
K7A801800B 256K x 36 & 512K x 18 Synchronous SRAM
K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM
K7A801809A 256Kx36 & 512Kx18 Synchronous SRAM
K7A801809B 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
K7A161800A 512K x 36 / x32 & 1M x 18 Synchronous SRAM
K7A161801A 512K x 36 / 32 & 1M x 18 Synchronous SRAM
K7A161831B 18MB B-DIE SYNC SRAM SPECIFICATION 100TQFP WITH PB / PB-FREE

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K7A803609A K7A801809A Document Title 256Kx36 & 512Kx18 Synchronous SRAM 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 1.0 History Initial draft 1. Final spec Release. Draft Date May. 24 . 2000 July. 03. 2000 Remark Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- July 2000 Rev 1.0 Free Datasheet http://www.datasheet4u.