Datasheet Details
| Part number | K7I641884M |
|---|---|
| Manufacturer | Samsung Semiconductor |
| File Size | 438.50 KB |
| Description | (K7I641884M / K7I643684M) 72Mb DDRII SRAM Specification |
| Datasheet |
 K7I641884M Datasheet
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General Description
Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input
Key Features
- 1.8V+0.1V/-0.1V Power Supply.
- DLL circuitry for wide output data valid window and future frequency scaling.
- I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
- Pipelined, double-data rate operation.
- Common data input/output bus.
- HSTL I/O.
- Full data coherency, providing most current data.
- Synchronous pipeline read with self timed late write.
- Registered address, control and data inpu.