Download the K7I643684M datasheet PDF.
This datasheet also covers the K7I641884M variant, as both devices belong to the same (k7i641884m / k7i643684m) 72mb ddrii sram specification family and are provided as variant models within a single manufacturer datasheet.
General Description
Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input
Key Features
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future frequency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
Pipelined, double-data rate operation.
Common data input/output bus.
HSTL I/O.
Full data coherency, providing most current data.
Synchronous pipeline read with self timed late write.
Note: The manufacturer provides a single datasheet file (K7I641884M_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for K7I643684M (Reference)
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K7I643684M K7I641884M 2Mx36 & 4Mx18 DDRII CIO b4 SRAM 72Mb DDRII SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) www.DataSheet4U.com INFORMATION IN THIS DO...
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& Pb-Free (RoHS compliant) www.DataSheet4U.com INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.
K7I643684M Datasheet
