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K7I163682B K7I161882B
Document Title
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Add the speed bin (-33, -30) 2. Delete the speed bin (-25, -13) 1. Change the Boundary scan exit order. 2. Correct the Overshoot and Undershoot timing diagram. 1. Add the speed bin (-25) 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 1. Change the Maximum Clock cycle time. 2. Correct the 165FBGA package ball size. 1. Add the power up/down sequencing comment. 2. Update the DC current parameter (Icc and Isb). 3. Change the Max. speed bin from -33 to -30. 1. Change the ISB1. Speed Bin -30 -25 -20 -16 1.0 2.0 1. Final spec release 1. Delete the x8 Org. 2.