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K7I323682M - 1Mx36 & 2Mx18 DDRII CIO b2 SRAM

Datasheet Summary

Description

on page 2 and add HSTL I/O comment 1.

Update current characteristics in DC electrical characteristics 2.

Change AC timing characteristics 3.

Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future freguency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
  • Pipelined, double-data rate operation.
  • Common data input/output bus.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Registered address, control and data inp.

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Datasheet Details

Part number K7I323682M
Manufacturer Samsung semiconductor
File Size 377.82 KB
Description 1Mx36 & 2Mx18 DDRII CIO b2 SRAM
Datasheet download datasheet K7I323682M Datasheet
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Full PDF Text Transcription

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K7I323682M K7I321882M Document Title 1Mx36-bit, 2Mx18-bit DDRII CIO b2 SRAM 1Mx36 & 2Mx18 DDRII CIO b2 SRAM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. Pin name change from DLL to Doff. 2. Vddq range change from 1.5V to 1.5V~1.8V. 3. Update JTAG test conditions. 4. Reserved pin for high density name change from NC to Vss/SA 5. Delete AC test condition about Clock Input timing Reference Level 6. Delete clock description on page 2 and add HSTL I/O comment 1. Update current characteristics in DC electrical characteristics 2. Change AC timing characteristics 3. Update JTAG instruction coding and diagrams 1. Add AC electrical characteristics. 2. Change AC timing characteristics. 3. Change DC electrical characteristics(ISB1) 1. Change the data Setup/Hold time. 2.
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