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K7D803671B K7D801871B
Document Title
8M DDR SYNCHRONOUS SRAM
256Kx36 & 512Kx18 SRAM
Revision History
Rev No. Rev. 0.0 Rev. 0.1 Rev. 0.2 History -Initial document. -ZQ tolerance changed from 10% to 15% -Stop Clock Standby Current condition changed from VIN=VDD-0.2V or 0.2V fixed to V IN =VIH or V IH -VDDQ Max. changed to 2.0V SA0, SA1 defined for Boundary Scan Order -Deleted -HC16 part(Part Number, Idd, AC Characterisctics) - Absolute Maximum ratings VDDQ changed from 3.13V to 2.825V - LBO input level changed from High/Low to VDDQ/VSS - Stop Clock Standby Current condition changed from K=Low, K=High to K=Low, K=Low - tCHQV/tCLQV changed from 0.1ns to 0.2ns for -33 part from 0.1ns to 0.2ns for -30 part from 0.1ns to 0.25ns for -25part - tCHQX/tCLQX changed from -0.3ns to -0.
K7I321882M Datasheet
