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K7I321882M - 1Mx36 & 2Mx18 DDRII CIO b2 SRAM

General Description

Pin Name K, K SA SA0, SA1 DQ CQ, CQ B1 B2 B3 G LBO Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (SA 0 = LSB) Synchronous Data I/O Differential Output Echo Clocks Load External Address Burst R/W Enable Single/Double Data Selection Asynchronous Output E

Key Features

  • and the timing waveforms regarding the burst controllability. - Recommended DC operating conditions for Clock added. - AC test conditions for V DDQ=1.8V and Single ended clock added. (AC Test Conditions 2) - Package thermal characteristics added. - Add-HC35 part(Part Number, Idd, AC Characteristics) - Absolute Maximum Rating VDDQ changed from 2.825V to 2.4V - V CM-CLK Min changed from 0.6V to 0.68V - Add-HC37 part(Part Number, Idd, AC Characteristics) Draft Data July. 2000 Aug. 2000 Oct. 2000 Re.

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Full PDF Text Transcription for K7I321882M (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K7I321882M. For precise diagrams, and layout, please refer to the original PDF.

K7D803671B K7D801871B Document Title 8M DDR SYNCHRONOUS SRAM 256Kx36 & 512Kx18 SRAM Revision History Rev No. Rev. 0.0 Rev. 0.1 Rev. 0.2 History -Initial document. -ZQ tol...

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Rev No. Rev. 0.0 Rev. 0.1 Rev. 0.2 History -Initial document. -ZQ tolerance changed from 10% to 15% -Stop Clock Standby Current condition changed from VIN=VDD-0.2V or 0.2V fixed to V IN =VIH or V IH -VDDQ Max. changed to 2.0V SA0, SA1 defined for Boundary Scan Order -Deleted -HC16 part(Part Number, Idd, AC Characterisctics) - Absolute Maximum ratings VDDQ changed from 3.13V to 2.825V - LBO input level changed from High/Low to VDDQ/VSS - Stop Clock Standby Current condition changed from K=Low, K=High to K=Low, K=Low - tCHQV/tCLQV changed from 0.1ns to 0.2ns for -33 part from 0.1ns to 0.2ns for -30 part from 0.1ns to 0.25ns

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