K7I321882M - 1Mx36 & 2Mx18 DDRII CIO b2 SRAM

Product Overview

Samsung semiconductor

Datasheet Details

Part number	K7I321882M
Manufacturer	Samsung semiconductor
File Size	270.13 KB
Description	1Mx36 & 2Mx18 DDRII CIO b2 SRAM
Datasheet	K7I321882M Datasheet
Additional preview pages of the K7I321882M datasheet.

Product details

Description

Pin Name K, K SA SA0, SA1 DQ CQ, CQ B1 B2 B3 G LBO Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (SA 0 = LSB) Synchronous Data I/O Differential Output Echo Clocks Load External Address Burst R/W Enable Single/Double Data Selection Asynchronous Output Enable Linear Burst Order Pin Name ZQ TCK TMS TDI TDO VREF VDD VDDQ VSS NC Pin Description Output Driver Impedance Control Input JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Dat

Features

and the timing waveforms regarding the burst controllability. - Recommended DC operating conditions for Clock added. - AC test conditions for V DDQ=1.8V and Single ended clock added. (AC Test Conditions 2) - Package thermal characteristics added. - Add-HC35 part(Part Number, Idd, AC Characteristics) - Absolute Maximum Rating VDDQ changed from 2.825V to 2.4V - V CM-CLK Min changed from 0.6V to 0.68V - Add-HC37 part(Part Number, Idd, AC Characteristics) Draft Data July. 2000 Aug. 2000 Oct. 2000 Re.

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Published: Apr 7, 2005 |